SRAM (Static Random Access Memory) is often integrated as part of a microprocessor IC (integrated circuit), a DSP (digital signal processor) IC or other SOCs (System on a Chip). In addition, SRAM may be fabricated as a stand-alone IC. Individual memory cells (bits) on an SRAM may fail for a variety of reasons. For example, a memory cell may fail to due to a “hard” failure. Hard failures may be caused by physical defects such as metal shorting two electrical nodes together or a void in a metal connection for example.
An individual memory may also fail due to a “soft” failure. Usually, a soft failure will occur in a memory cell of an SRAM due to voltage conditions applied during read and write cycles. These voltage conditions at the memory arrays may be due to variations in the supply voltage and variations in process parameters for example. These variations in process parameters include variation of threshold voltages (Vt) and variation in leakage current for example. Variation in Vt, for example, may occur due to fluctuations in the doping of a transistor or the effective length of a transistor.
Hard and soft memory cell failures may be fixed using redundant memory cells that are added to an IC specifically to replace memory cells that fail. Adding redundant memory cells however requires more area to be used on an IC. Increasing the size of an IC usually increases the cost of the IC. As a result, the amount of redundancy used to repair memory cell failures is kept as small as possible. While memory cell failures caused by hard failure usually need to be corrected using redundant bits, memory cell failures caused by soft failure may be corrected without using redundant memory cells.
When a memory cell failure occurs due to a soft failure, circuit techniques or “assists” may be used to correct the memory cell failures. These techniques usually increase or decrease a voltage applied to an individual memory cell. For example, boosting (increasing) the voltage on a word line during a write cycle can improve the write margin of an SRAM memory cell. Lowering the voltage on a bit line below VSS during a write cycle can also improve the ability to write to an SRAM memory cell. These and other circuit techniques will be explained in more detail in the specification that follows.
By first identifying soft (memory cell) failures in an SRAM and then fixing the soft (memory cell) failures using circuits assists, the amount of redundancy required on an SRAM may be reduced and as a result lower the cost of an IC.